As integrated circuit technology advances, circuit elements and interconnections on substrates have become increasingly more dense. In order to reduce the likelihood of unwanted interactions between the circuit elements on the integrated circuit substrate, insulating regions are provided in trenches/gaps located on the integrated circuit substrates to physically and/or electrically isolate the circuit elements and conductive lines associated therewith. However, as circuit densities continue to increase, the widths of the trenches continue to decrease. Thus, aspect ratios, i.e. the height of the trench divided by the width of the trench, of the trenches/gaps continue to increase. As a result, it may become increasingly difficult to fill the narrow trenches, which may lead to unwanted voids and discontinuities in the insulating regions.
Conventional methods of filling trenches having high aspect ratios may include high-density plasma (HDP) oxide deposition. Typical HDP deposition processes employ chemical vapor deposition (CVD) with a gas mixture containing, for example, oxygen, silane, and argon to achieve simultaneous dielectric etching and deposition. In an HDP process, an RF bias may be applied to an integrated circuit substrate in a reaction chamber. Some of the gas molecules (particularly argon) in this gas mixture are ionized in the plasma and accelerate toward the wafer surface when the RF bias is applied to the integrated circuit substrate. Material may thereby be sputtered when the ions strike the surface of the integrated circuit substrate. Accordingly, dielectric material deposited on the surface of the integrated circuit substrate may be simultaneously sputter-etched to enable the trench to remain open during the deposition process.
FIGS. 1A through 1D illustrate, in more detail, the simultaneous etch and deposition (etch/dep) process described above. As illustrated in FIG. 1A, SiO2, formed from silane (SiH4) and oxygen (O2), is deposited on the surface of an integrated circuit substrate 100 to fill the gap/trench 110 between the circuit elements 120. As the SiO2 is deposited, charged ions may impinge on the SiO2 or dielectric layer 125 (FIG. 1B), thereby simultaneously etching the SiO2 layer. However, because the etch rate at about 45° is approximately three to four times the etch rate on the horizontal surface, 45° facets 130 may form at the corners of the circuit elements 120 during the deposition process, as illustrated in FIG. 1B. FIGS. 1C and 1D illustrate a conventional process of filling the gap 110 by the simultaneous etching and deposition of SiO2.
The etch/dep ratio may be optimized such that facets 130 remain at the corners of circuit elements 120 throughout the HDP deposition process. However, as illustrated in FIG. 2A, if the etch/dep ratio is decreased, facets 130 may begin to move away from the corners of the circuit elements 120, and cusps 210 may begin to form on sidewalls of gap/trench 110. Cusp 210 formation may be due to some of the etched SiO2 being redeposited on opposing surfaces through line-of-sight redeposition, even though most of the etched SiO2 is emitted back into the plasma and pumped out of the reaction chamber. This redeposition may increase as the distance between opposing surfaces decreases. Therefore, as the facets 130 move away from the corners of the circuit elements 120, the line-of-sight paths may be shortened, resulting in increased sidewall redeposition. At a certain point in the process, the cusps 210 will meet and may prevent further deposition below the cusps. When this occurs, a void 220 may be created in dielectric layer 125, as illustrated in FIG. 2B. On the other hand, if the etch/dep ratio is increased, the etching component can etch or “clip” material from the corners of elements 120, and thereby possibly damage the circuit elements 120 and introduce etched contaminants 310 into dielectric layer 125 as illustrated in FIGS. 3A and 3B.
The etch/dep ratio may be controlled by varying the flow rate of silane or other process gases, which may affect the deposition rate, or by varying either the power supplied to the wafer for biasing or the flow rate of argon, which may affect the sputter etch rate. Etch rates are typically increased by increasing the flow rate of argon, which is used to promote sputtering, rather than increasing power and expending large amounts of energy. Typical argon flow rates for HDP deposition range from 30%–60% or more of the total process gas flow rate. By optimizing the etch/dep ratio, gaps with aspect ratios of up to about 3.0:1.0 may be filled without void formation. However, as illustrated in FIG. 3B, filling higher gap aspect ratios may result in voids 410 due to cusps 420 prematurely closing the gap/trench even if the etch/dep ratio is optimized to 1 at the element corners. As discussed above, this may be mainly due to the shortened line-of-sight path between opposing sidewalls. If the etch rate is increased to keep the gaps open longer, undesirable corner clipping can occur.
Methods for filling trenches having high aspect ratios are discussed in U.S. Pat. No. 6,395,150 entitled VERY HIGH ASPECT RATIO GAPFILL USING HDP. The method described therein attempts to solve problems associated with the conventional methods discussed above by replacing argon gas with helium gas having a small atomic weight relative to argon gas.
In particular, FIGS. 4A through 4D are cross-sectional views illustrating methods described in U.S. Pat. No. 6,395,150. Referring now to FIG. 4A, circuit elements 520 are formed on an integrated circuit substrate 100. The circuit elements 520 may define gaps/trenches 510 on the integrated circuit substrate 100. The circuit elements 520 may be, for example, transistors, conductors, or interconnects. A trench 510 having a high aspect ratio, typically greater than 2.5:1, is filled using HDP deposition, where sputtering is accomplished with Helium (He) and Oxygen (O2). During the initial stages of the process, 45° facets 530 may form at the corners of circuit elements 520, as illustrated in FIG. 4A. Due to the reduction in the etching component, the facets 530 begin to move away from the corners of circuit elements 520 as more material deposits on the surfaces to form the SiO2 or dielectric layer 525, as illustrated in FIGS. 4B and 4C.
Furthermore, by replacing argon (Ar) with helium (He) the sidewall redeposition may be reduced. Due to the reduction in sputtering component, much less material may be available to redeposit on sidewalls 540 and facets 530, as illustrated in FIGS. 4B and 4C. As a result, cusp formation may be reduced, and the facets 530 may move away more slowly from the corners of the circuit elements 520. Thus, due to the decreased sidewall deposition, high aspect ratio gaps may not close prematurely even though the facets 530 move away from the corners. As illustrated in FIG. 4D, high aspect ratio gaps 510 may be filled without void formation or clipping.